The present invention relates to differential amplifiers and, more particularly, to a complementary self-biased differential amplifiers having DC hysteresis.
Complementary self-biased differential amplifiers (CSDA) are CMOS differential amplifiers having an input common-mode range that is relatively limited. The CDSA is characterized by its self-biasing through negative feed-back. In addition, CDSAs are completely complementary where each n-type device operates in push-pull fashion with a corresponding p-type device.
As shown in FIG. 1, a CSDA includes two complementary differential amplifiers connected together having the input drains connected to one another. As shown transistors MN1, MN2, and MN3 comprise a first amplifier and MP1, MP2, MP3, and MP4 comprise a second amplifier coupled together. In order to bias the circuit in a stabilized fashion, the current through transistors MN2, MP2, and MP3 is made the same by coupling the gates of transistors MN2, MP2, and MP3 to the internal voltage node Vbias. This self-biasing of the amplifier creates a negative-feedback loop that stabilizes the bias voltages in the case of any variations in processing parameters or operating conditions.
As a result of their distinctive design, CDSAs include several performance enhancements over conventional CMOS differential amplifier designs. CDSAs include active-region biasing that is less sensitive to variations in processing, temperature and supply. Furthermore, CDSAs have the capability of supplying switching currents that are significantly greater than the quiescent bias current. CDSAs also include nominal doubling of differential-mode gain.
All of these features make the CDSA a prime candidate for comparator applications where precision, high speed, ease of interfacing to ordinary logic gates, and consistently high production yields are required. One such application is in commercial digital CMOS VLSI integrated circuits.
Complications, however, arise in applications where the CDSA is used in a backplane as a differential pair input receiver when excessive noise levels exist on the backplane. In cases where the backplane is properly terminated to match the effective characteristic impedance of the bus as shown in FIG. 2, there may be a small amount of overshoot and undershoot in the signal. Thus, the upper and lower noise margins, A and B, are large leaving room for noise that may be present on the backplane. As shown in the present example, the voltage reference is 1 volt which is the voltage necessary to be applied at the input of the amplifier to switch the output from low to high or from high to low depending upon the present state of the amplifier output.
Problems arise, however, in the case where the backplane is overly terminated. As shown, an overshoot and undershoot occurs near the transition during a low-to-high and a high-to-low transition. The undershoots and overshoots generate smaller upper and lower noise margins, respectively, for input receivers where the backplane is over or under terminated as opposed to the backplane that is properly terminated. Specifically, regions A and B represent the upper and lower noise margin for the properly terminated backplane; and regions C and D represent the upper and lower noise margins for the overly terminated backplane. Regions A and B are comparatively larger than regions C and D due to the reasons described above. Thereby, a smaller margin for noise exists when the backplane is overly terminated. The same holds true when the backplane is unevenly loaded.
Thus, there exists a need for a CDSA having the ability to maintain an adequate noise margin in applications where the CDSA is used for an input receiver of a backplane whether the backplane is properly terminated, overly terminated or unevenly loaded.
To address the above-discussed deficiencies of the complementary self-biased differential amplifier, the present invention teaches a differential pair input receiver including a complementary self-biased differential amplifier, wherein the complementary self-biased differential amplifier has an input, a reference output node, and a dynamic voltage reference node. A dynamic hysteresis voltage reference circuit connects between the reference output node and the dynamic voltage reference node to provide a reference voltage at the dynamic voltage reference node. The reference voltage serves as a threshold for the complementary self-biased differential amplifier, such that the output transitions from high-to-low and low-to-high when the input is equal to the reference voltage. Furthermore, the dynamic hysteresis voltage reference circuit adjusts the reference voltage to provide a different threshold for each respective transition from high-to-low and from low-to-high, increasing the noise margins for each.
Advantages of this design include but are not limited to a differential pair input receiver having variable reference voltages that may be customized by the designer. As a result, this design for the differential pair input receiver may increase the noise margins. Thus, providing a more stable circuit design.